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Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHW35NQ20T
FEATURES
* 'Trench' technology * Very low on-state resistance * Fast switching * Low thermal resistance
SYMBOL
d
QUICK REFERENCE DATA VDSS = 200 V ID = 35 A
g
RDS(ON) 70 m
s
GENERAL DESCRIPTION
N-channel enhancement mode field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHW35NQ20T is supplied in the SOT429 (TO247) conventional leaded package.
PINNING
PIN 1 2 3 tab gate drain source drain DESCRIPTION
SOT429 (TO247)
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 200 200 20 35 25 140 250 175 UNIT V V V A A A W C
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 35 A; tp = 100 s; Tj prior to avalanche = 25C; VDD 50 V; RGS = 50 ; VGS = 10 V; refer to fig:15 MIN. MAX. 462 UNIT mJ
IAS
-
35
A
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHW35NQ20T
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. in free air 45 MAX. 0.6 UNIT K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance Gate source leakage current Zero gate voltage drain current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 17 A VGS = 10 V; ID = 17 A; Tj = 175C VGS = 10 V; VDS = 0 V VDS = 200 V; VGS = 0 V; Tj = 175C ID = 35 A; VDD = 160 V; VGS = 10 V MIN. 200 178 2.0 1.0 TYP. MAX. UNIT 3.0 60 2 0.05 77 16 28 22 100 80 90 3.5 4.5 7.5 4570 370 160 4.0 6 70 203 100 10 500 V V V V V m m nA A A nC nC nC ns ns ns ns nH nH nH pF pF pF
VDD = 100 V; RD = 2.7 ; VGS = 10 V; RG = 5.6 Resistive load Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 35 A; VGS = 0 V IF = 20 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V TYP. MAX. UNIT 0.85 160 1.0 35 140 1.2 A A V ns C
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHW35NQ20T
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
1
Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2
0.1
0.1 0.05 0.02 P D single pulse T
0.01
tp
D = tp/T
0.001 1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A) Tj = 25 C 35 30 25 5V 20 15 10 5 4.2 V 4.8 V 4.6 V 4.4 V 8V VGS = 10V 6V 5.2 V
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
40
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); VGS 10 V
Peak Pulsed Drain Current, IDM (A) 1000
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS)
0.2 0.18 RDS(on) = VDS/ ID 100 tp = 10 us
Drain-Source On Resistance, RDS(on) (Ohms) 4.4 V 4.2 V 4.6 V Tj = 25 C
0.16 0.14 0.12 100 us 0.1 0.08 5V 5.2 V 6V VGS = 10V 4.8 V
10 D.C. 1 ms 10 ms 100 ms 1 1 10 100 Drain-Source Voltage, VDS (V) 1000
0.06 0.04 0.02 0 0 5 10 15 20 25 Drain Current, ID (A) 30 35 8V
40
Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID)
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHW35NQ20T
Drain current, ID (A) 40 VDS > ID X RDS(ON) 35 30 25 20 15 10 5 0 0 1 2 3 4 5 6 Gate-source voltage, VGS (V) 175 C Tj = 25 C
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
Threshold Voltage, VGS(TO) (V) maximum typical
minimum
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics. ID = f(VGS)
Transconductance, gfs (S) VDS > ID X RDS(ON) Tj = 25 C
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Drain current, ID (A)
50 45 40 35 30 25 20 15 10 5 0
1.0E-01
1.0E-02
175 C
1.0E-03
minimum typical
1.0E-04 maximum 1.0E-05
1.0E-06
0 5 10 15 20 25 Drain current, ID (A) 30 35 40
0
0.5
1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V)
4
4.5
5
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C)
10000
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C
Capacitances, Ciss, Coss, Crss (pF) Ciss
1000 Coss
100 Crss
10 0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHW35NQ20T
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Gate-source voltage, VGS (V) ID = 35 A Tj = 25 C VDD = 40 V 100
Maximum Avalanche Current, IAS (A)
25 C VDD = 160 V 10
Tj prior to avalanche = 150 C
0
10
20
30
40 50 60 70 Gate charge, QG (nC)
80
90
100
1 0.001
0.01
0.1 Avalanche time, tAV (ms)
1
10
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load
Source-Drain Diode Current, IF (A) 40 35 30 175 C 25 20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Tj = 25 C VGS = 0 V
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHW35NQ20T
MECHANICAL DATA
Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247
SOT429
E P
A A1 q S
R D Y
L1(1) Q b2 L
1
2 b b1 e e
3 wM c
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 5.3 4.7 A1 1.9 1.7 b 1.2 0.9 b1 2.2 1.8 b2 3.2 2.8 c 0.9 0.6 D 21 20 E 16 15 e 5.45 L 16 15 L1
(1)
P 3.7 3.3
Q 2.6 2.4
q 5.3
R 3.5 3.3
S 7.5 7.1
w 0.4
Y 15.7 15.3
6 4
17 13
4.0 3.6
Note 1. Tinning of terminals are uncontrolled within zone L1. OUTLINE VERSION SOT429 REFERENCES IEC JEDEC TO-247 EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07 99-08-04
Fig.16. SOT429; pin 2 connected to mounting base
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor
PHW35NQ20T
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
7
Rev 1.000

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